1. Field of the Invention
This invention generally relates to a manufacturing method of a semiconductor device and more particularly to a manufacturing method for producing a complementary metal oxide semiconductor transistor, such as, a C-MOS transistor.
2. Description of the Prior Art
C-MOS transistors must be constructed to high standards of performance. FIGS. 1A to 1G respectively illustrate an example of a prior art manufacturing method of the C-MOS transistor. In accordance with the prior art manufacturing method, as shown in FIG. 1A, on a major surface of a semiconductor substrate 1 of a second conductivity type, for example, N-type at portions where N channel and P channel MOS transistors are respectively to be formed, there are respectively formed thin insulating layers (for example, SiO.sub.2 layers) 2 which will serve as gate insulating layers. Selectively formed on the respective insulating layers 2 are polycrystalline silicon layers 3, 3' containing, for example, phosphorus which will become gate electrodes. A first conductivity type, namely, P-type island region 4 is formed in the substrate and field oxide layers (SiO.sub.2 layers) 5 having large thicknesses are formed on the major surface of the substrate 1 at field portions by selective oxidation thereof. In the portions of the substrate 1 beneath the field oxide layers 5, channel stopper regions 6 may be previously formed. Then, as shown in FIG. 1B, the N channel side is masked with a photoresist layer 7 and then B+ ions of boron are implanted into the substrate 1 with an implantation energy of 50 KeV and at a dosage of 5.times.10.sup.14 cm.sup.-2 to form a source region 8S and a drain region 8D for the P channel. Then, as shown in FIG. 1C, the P channel is masked with a photoresist layer 7 and P.sup.+ phosphorus ions are implanted into the substrate 1 with an implantation energy of 80 KeV and at a dosage of 5.times.10.sup.15 cm.sup.-2 to form a source region 9S and a drain region 9D for the N channel. The semiconductor device is then subjected to an annealing treatment and an oxidation treatment so as to form oxide layers (SiO.sub.2) 10 on the surfaces of both of the polycrystalline silicon layers 3 and 3'. The oxide layers 10 are used to prevent, for example, an arseno-silicate glass layer which will be formed later and the polycrystalline silicon layers 3 and 3' which contains phosphorus from reacting with each other. Then, as shown in FIG. 1E, a silicate glass layer 11 such as arseno-silicate glass phosphorus silicate glass or the like is deposited on the entire surface of the semiconductor device by the CVD (chemical vapor deposition) method. Then contact window apertures are formed through the silicate glass layer 11, and glass-flow treatment is carried out. The first wiring 12 of Al is formed, thus forming the C-MOS transistors comprising the N channel MOS(N-MOS) transistor and the P channel MOS (P-MOS) transistor, as shown in FIG. 1F.
Thereafter, when double layer wiring is formed, as shown in FIG. 1G, an insulating layer 13 made of, for example, silicate glass for insulation between adjacent layers is deposited on the first Al wiring 12 and through the insulating layer 13 contact window apertures are formed. Then, a second wire conductor 14 made of Al is formed and an insulation protective layer 15 is formed on the entire surface of the semiconductor device thus formed.
Such prior art manufacturing method, however, have the following disadvantages. When the source region 9S and the drain region 9D of the N channel side are formed by the ion implantation technique, if P.sup.+ phosphorus ions are used, there is no problem because the projection range R.sub.p is large. However, when the source region 9S and the drain region 9D of the N channel side are formed with a fine pattern As.sup.+ arsenic ions are inevitably used. In this case, since the projection range R.sub.p of arsenic ions As.sup.+ are small, it is very difficult to carry out ion implantation through the thin insulating layers (gate oxide layers) 2 which have a thickness of about 400 .ANG. during the process shown in FIG. 1C.
When the source region 8S and the drain region 8D of the P channel side are formed by the ion-implantation technique, polycrystalline silicon containing phosphorus (polycrystalline silicon containing boron B is difficult to use in view of BT (bias-temperature) stability and the stability of threshold voltage, and the polycrystalline silicon layer 3 of the gate portions which serves as the mask for the source and drain regions ions of, boron are implanted by a self-alignment process shown in FIG. 1B, but it will have a dosage of 5.times.10.sup.14 cm.sup.-2. Inherently, in order to lower the resistance value of the source region 8S and the drain region 8D of the P channel side, B.sup.+ ions of boron having a dosage of 5.times.10.sup.5 cm.sup.-2 are necessary. As a result, the resistance value of the source and drain regions 8S and 8D of the P channel side becomes as high as about 200 .OMEGA./.epsilon. with the result that the characteristics of the P channel MOS transistor are deteriorated.
Further, since B.sup.+ ions of boron are implanted into the polycrystalline layer 3 at the dosage of 5.times.10.sup.14 cm.sup.-2, the resistance value of the polycrystalline silicon layer 3 of the gate portion is raised. In addition, work function .phi.ms of the gate is changed and thus the threshold voltage becomes variable in different components.